# Argus 3000/5000/7000 (Monochrome) Hacking – 1

The system design of these moving map displays is surprisingly compact. It is a streamlined 68000 system with a CRT display. It reminded me of those early Z80 computers.

Version 5.0 has a different PCB design. But I believe the only major change is in the ROM section.

### Python Script to interleave the two halves of the ROM dump

import itertools
f1 = open('ARGUS7000_3.2_U2.bin','rb');
f2 = open('ARGUS7000_3.2_U3.bin','rb');
fout = open('ARGUS7000_3.2.bin','wb+');
f1.close();
f2.close();
fout.write(bytearray(itertools.chain(*zip(b1, b2))))
fout.close();

### Memory Map:

ADC and 6845 are supposed to be read-only, but for some reason, the decoder PAL doesn’t care.

With the memory map acquired, the ROM can be disassembled like a generic 68k system. There doesn’t seem to be any unusual design.

### RS232 Terminal Mode (Firmware Version 5.0+)

Starting from firmware 5.0, the Argus maps all have a special mode built-in that allows the device to operate as a terminal. To enter this mode, do the following:

1. Hold ENR & AUX keys during power-on, until you see “SETUP MODE ENABLED” during boot-up
2. Tripple click “AUX” to enter the setup menu
3. In the “LRN TYPE SELECTION” page, select “ASCII Port A” (Transmit ASCII) or “HEX Port A” (Transmit ASCII encoded hex)
4. Click “PAGE” until you see “DATA FORMAT SELECT”, configure the RS-232 parameters as you want. (Note: Argus doesn’t support hardware handshaking. It only supports XON/XOFF)

Now the device is ready for receiving. The following escape sequences are available:

1. This is an paraphrase from the Argus Reference Manual
2. The screen pixels are not square, they are 2:3. This will affect how an arc is drawn

Some test code to plot that Sanae-san image

import serial
import time

from PIL import Image
import matplotlib.pyplot as plt
import numpy as np
simg = Image.open('Th12Sanae_bw.png')
plt.imshow(simg)
simg_b = np.array(simg.convert("1"))

ser = serial.Serial('COM5',38400)
print(ser.name)
ser.write('\x1b[J'.encode('ANSI'))
ser.write('\x1b[11m'.encode('ANSI'))
ser.write('\x1b[50m'.encode('ANSI'))

#ser.write('\x1b[256;128a'.encode('ANSI'))
ser.write('\x1b[J'.encode('ANSI'))
ser.write('\x1b[70m'.encode('ANSI'))
ser.write(('\x1b['+str(0xF)+'b').encode('ANSI'))

for i in range(256):
s = simg_b[:,i]
sl = False
p = 0
pl = 0
for c in s:
p = p+1
if(sl!=c):
if(c==False):
ser.write(('\x1b['+str(pl)+';'+str(i)+'a').encode('ANSI'))
ser.write(('\x1b['+str(p-1)+';'+str(i)+'c').encode('ANSI'))
sl = c
pl = p

ser.close()

The DRAMs, as you’d expect, are addressed in the “CAS/RAS” way: Their 16-bits of total address width is issued twice by the DRAM PAL controlled MUX. The total DQ bit width is 16bits. (hence no A0 from the CPU)

Screen’s Horizontal Lines – CRTC’s Vertical: 512 bits in total, Shift Register contains [15:0] = 16 bits, the rest is addressed by MA[4:0]

Screen’s Vertical Lines – CRTC’s Horizontal: 256 scanlines in total, addressed by {MA[9:5],RA[2:0]} (probably, not verified).

Paging is probably controlled by MA[12:10] by modifying the R12 – Starting High Address Register

### DRAM Controller PAL

The DRAM addressing and refreshing is controlled by a single PAL chip. This is quite an elegant design considering how limited the PALs were at that time. The PAL is encrypted, so I can’t read the content easily with my TL866. But here’s something very close.

This National Semi DP84322 DRAM controller chip seems to be a relabeled PAL. The Argus implementation added 3bit high address decoding and MUX control logic on top of this.