Argus 3000/5000/7000 (Monochrome) Hacking – 1

The system design of these moving map displays is surprisingly compact. It is a streamlined 68000 system with a CRT display. It reminded me of those early Z80 computers.

CPU Boards
XROM (Map Data) Board
PCB vs. Patent US4896154 / US5057835
Firmware Version 3 PCB Worksheet (including video timing, port pinout, etc. Click to zoom in)

Version 5.0 has a different PCB design. But I believe the only major change is in the ROM section.

Python Script to interleave the two halves of the ROM dump

import itertools
f1 = open('ARGUS7000_3.2_U2.bin','rb');
f2 = open('ARGUS7000_3.2_U3.bin','rb');
fout = open('ARGUS7000_3.2.bin','wb+');
b1 = f1.read();
b2 = f2.read();
f1.close();
f2.close();
fout.write(bytearray(itertools.chain(*zip(b1, b2))))
fout.close();

Unfortunately, all pages of the ROM are copyrighted, I can’t offer a download link of them.

Memory Map:

Processor A[23:21]R/WCEn generated
3’b000 ($0xxxxx)RSystem ROM
3’b001 ($2xxxxx)R244 (Keyboard/Cassette Input Latch)
3’b010 ($4xxxxx)RExternal ROM (Map Data)
3’b011 ($6xxxxx)RW ?ADC
3’b100 ($8xxxxx)RW68681 (RS232, GPIO)
3’b101 ($Axxxxx)RW ?6845 (CRTC)
3’b110 ??Unknown
3’b111 ($Fxxxxx)RWDRAM
Memory Map, reverse engineered from the decoder PAL

ADC and 6845 are supposed to be read-only, but for some reason, the decoder PAL doesn’t care.

With the memory map acquired, the ROM can be disassembled like a generic 68k system. There doesn’t seem to be any unusual design.

Some Disassembly (Version 3.2)

Hardcoded CRTC init code
Entry point of the “Print to CRT display” function

RS232 Terminal Mode (Firmware Version 5.0+)

Starting from firmware 5.0, the Argus maps all have a special mode built-in that allows the device to operate as a terminal. To enter this mode, do the following:

  1. Hold ENR & AUX keys during power-on, until you see “SETUP MODE ENABLED” during boot-up
  2. Tripple click “AUX” to enter the setup menu
  3. In the “LRN TYPE SELECTION” page, select “ASCII Port A” (Transmit ASCII) or “HEX Port A” (Transmit ASCII encoded hex)
  4. Click “PAGE” until you see “DATA FORMAT SELECT”, configure the RS-232 parameters as you want. (Note: Argus doesn’t support hardware handshaking. It only supports XON/XOFF)

Now the device is ready for receiving. The following escape sequences are available:

ESC SequenceFunction
<ESC>[1?Report the model number
<ESC>[2?Report the serial number
<ESC>[3?Report software version
<ESC>[4?Report cursor position
<ESC>[5?Report CRT brightness (CE only)
<ESC>[NAMove the cursor up “N” lines
<ESC>[NBMove the cursor down “N” lines
<ESC>[NCMove the cursor right “N” characters
<ESC>[NDMove the cursor left “N” characters
<ESC>[Y;XHMove the cursor to character row “Y” col “X”
<ESC>[JClear screen and cursor position
<ESC>[KErase from the cursor position to the end of the line
<ESC>[mAll character attributes off, set to “monospace” font. Set color to yellow, Set repeat rate to 1pps
<ESC>[7mSet reverse video on all following characters
<ESC>[31mSet foreground color to red
<ESC>[32mSet foreground color to green
<ESC>[33mSet foreground color to yellow
<ESC>[sSave cursor position
<ESC>[uRestore cursor position
<ESC>[10mSet to “small” font
<ESC>[11mSet to “medium” font
<ESC>[12mSet to “large” font
<ESC>[13mSet to “monospace” font
<ESC>[14mSet to “giant” font
<ESC>[BBhSet CRT brightness to “BB” (CE only)
<ESC>[TTiSet repetition rate to “TT”*20ms
<ESC>[5NmDraw to screen “N”, N=0~3
<ESC>[6NmCopy screen “N+1” to “N”, N=0~2
<ESC>[77mManual brightness adjust mode (CE only)
<ESC>[78mSoftware brightness adjust mode (CE only)
<ESC>[70mDrawing mode “OR”
<ESC>[72mDrawing mode “XOR”
<ESC>[PPPPPPPPb Set drawing pattern to “PPPPPPPP” ( The feature seems to be broken)
<ESC>[73mDrawing mode “Pattern MOVE”
<ESC>[74mDrawing mode “Pattern OR”
<ESC>[76mDrawing mode “Pattern XOR”
<ESC>[Y;XaSet cursor to “X,Y”
<ESC>[Y;XcDraw a line from cursor to “X,Y”
<ESC>[S;E;RdDraw an arc centered at the cursor, with starting angle “S”, ending angle “E”, radius “R”
<ESC>[Y;XeDraw a filled box from cursor to “X,Y”
<ESC>[Y;XfDraw a outlined box from cursor to “X,Y”
<ESC>[80mDisable scrolling
<ESC>[79mEnable scrolling
<ESC>[YLL;XLL;YUR;XURgSet clipping limits, default value: YLL=488, XLL=1; YUR=1; XUR=256
<ESC>[81mSet character height to one line
<ESC>[82mSet character height to the minimum of the current font
  1. This is an paraphrase from the Argus Reference Manual
  2. The screen pixels are not square, they are 2:3. This will affect how an arc is drawn

Some test code to plot that Sanae-san image

import serial
import time

from PIL import Image
import matplotlib.pyplot as plt
import numpy as np
simg = Image.open('Th12Sanae_bw.png')
plt.imshow(simg)
simg_b = np.array(simg.convert("1"))


ser = serial.Serial('COM5',38400)
print(ser.name)
ser.write('\x1b[J'.encode('ANSI'))
ser.write('\x1b[11m'.encode('ANSI'))
ser.write('\x1b[50m'.encode('ANSI'))

#ser.write('\x1b[256;128a'.encode('ANSI'))
ser.write('\x1b[J'.encode('ANSI'))
ser.write('\x1b[70m'.encode('ANSI'))
ser.write(('\x1b['+str(0xF)+'b').encode('ANSI'))

for i in range(256):
    s = simg_b[:,i]
    sl = False
    p = 0
    pl = 0
    for c in s:
        p = p+1
        if(sl!=c):
            if(c==False):
                ser.write(('\x1b['+str(pl)+';'+str(i)+'a').encode('ANSI'))
                ser.write(('\x1b['+str(p-1)+';'+str(i)+'c').encode('ANSI'))
            sl = c
            pl = p

ser.close()

VRAM Address

CPU
Addr Bus
(S=00)
CPU
Addr Bus
(S=01)
CRTC
Addr
(S=10)
CRTC
Addr
(S=11)
DRAM
Addr
(Y)
A8A9RA2MA5A0
A7A16RA1MA12A1
A6A15RA0MA11A2
A5A14MA4MA10A3
A4A13MA3MA9A7
A3A12MA2MA8A4
A2A11MA1MA7A5
A1A10MA0MA6A6

The DRAMs, as you’d expect, are addressed in the “CAS/RAS” way: Their 16-bits of total address width is issued twice by the DRAM PAL controlled MUX. The total DQ bit width is 16bits. (hence no A0 from the CPU)

Screen’s Horizontal Lines – CRTC’s Vertical: 512 bits in total, Shift Register contains [15:0] = 16 bits, the rest is addressed by MA[4:0]

Screen’s Vertical Lines – CRTC’s Horizontal: 256 scanlines in total, addressed by {MA[9:5],RA[2:0]} (probably, not verified).

Paging is probably controlled by MA[12:10] by modifying the R12 – Starting High Address Register

DRAM Controller PAL

The DRAM addressing and refreshing is controlled by a single PAL chip. This is quite an elegant design considering how limited the PALs were at that time. The PAL is encrypted, so I can’t read the content easily with my TL866. But here’s something very close.

Logic Diagram of DP84322

This National Semi DP84322 DRAM controller chip seems to be a relabeled PAL. The Argus implementation added 3bit high address decoding and MUX control logic on top of this.

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