Part3. LED Magic
LED numeric display is the icon of HP classics. With just a single 5-bit register inserted, how could they design such a full-featured, flicker-free and properly PWM’d
Sorry for such a long quiescence. Originally I was planning to actually make a board that drives the LED display before writing anything. Unfortunately, since quarter a year ago, I’m completely occupied by all sorts of things, and the plan is delayed forever. I’ll try if I’m free at some point in the future.
This is the first article written in the new “Gutenberg” WordPress editor. Noice!
(The top image is a part of an advertisement of HP calculators. Cropped to fit in.)
Section 1: Driving LEDs – Harder than you think
Let’s begin with the most basic topic: how would you drive an LED?
LEDs are basically diodes that pop photon when you pump energy into their p-n junction. Without digging too much into semiconductor physics, we can depict its property with a simple model.
The right part is referred to as “the DC path”, usually (unless you’re using some special diodes such as the tunnel diode) we consider it to be directional (when reverse biased, there won’t be any current through it). The junction Vj –
The left part is the AC path. Cj, which means Junction Capacitance, varies with the input voltage. This effect allows diodes to be used as voltage-controlled capacitors, which is usually utilized by variable frequency oscillators.
LEDs have very similar characteristics. Normally we consider the voltage drop of a forward-biased silicon diode to be 0.7V. LEDs usually have 1.2~4.0V drops.
Well, how to drive an LED? Ask a person who has most basic EE knowledge such a question, you’ll get such an answer:
The LED works great, but there’s an issue: If we do the math, the LED consumes 40mW, meanwhile, the 150Ω resistor consumes 60mW. Terrible! Normally when we’re talking about plug-powered electronics, this is good enough. However, thinking about throwing away 60% of the energy in a handheld, which, in this particular case, spends the most power driving the LED display: This is unacceptable.
How about driving it with a PWM signal? It indeed saves a lot of power. But since the diode is strongly nonlinear, at the high level of the PWM driving signal, the diode consumes a tremendous amount of current, even worse, the current is not necessarily well defined, especially for those earlier LEDs. In all, PWM is a way to dim LEDs easily, but it doesn’t save much power, nor is it relyable.
Adding a damper can average the PWM’d voltage out, giving a smooth output. This prevents destroying the LED by striking it with overcurrent over and over again. A charged-up inductor, for example, in a short time can be seen as a “current source”. It seems that we can use the inductor in some switched way to provide a perfect, current limited PWM source for driving an LED.
This is actually the principle of DC-DC converters. If you introduce a feedback loop into the circuit, you can dynamically adjust the
Section 2: Led’ing the -hp- way
Now let’s see how HP approaches the problem of driving the display of its handhelds, an array of LEDs.
First thing first, the power distribution in an HP calculator is more complicated than modern products and is worth an additional article to elaborate. The fact that they had mixed more than three technologies in a single product means there are more than 5 voltages that may present!
Vbsw :Battery Voltage, ≈4V Vss :PMOS Positive Supply, 6.0V Vgg :PMOS Negative Supply, -12.0V Vcc :Kathode Driver Supply, +8.2V Gnd: 0V
The processor chips are PMOS logic. (Here I’m not going to talk about that in detail.) One thing to notice is that: in order to run these chips fast enough and can output enough energy, they had decided to drive it with 18V – a very high voltage (from Vgg(-12V) to Vss(+6V)), which seems crazy by today’s standard but quite conventional in the early days.
The GND pin on these chips serves as a voltage clamping reference. In this way, they can generate a signal at the output of these PMOS chips that can be accepted by the bipolars. Internally the PMOS logic has nothing to do with this pin.
Now, let’s focus on the display section:
The display drivers are bipolar integrated circuits that contain:
- hp 1820-0853 Anode Driver / Clock Oscillator /
Clock Divider ( 2-phase clock generator ) / Voltage Reference and Comparator. It runs between Gnd and Vbsw.
- hp 1820-0854 Kathode Driver. It runs between Vbsw and Vcc. This chip is floating.
- hp 1820-0855 Clock Amplifier /
Voltage Shifter (from TTL 0 ~ +4V to PMOS -12V ~ +6V)
We’ll dig into the chips later. Now take a look at the display matrix.
The design utilizes inductors as a temporary current limiter: At first, the Anode transistors are switched on, current flows through L, accumulating magnetic energy in the inductor. Since this path is a low resistance path, only little energy is wasted, and there is not enough voltage to turn on the LED.
After the inductor is charged with magnetic energy, the Anode is turned off. A flyback voltage across the inductor is generated in order to maintain the current. Thence the LED turns on and shines for a brief 6us.
This design is very interesting, but not the best part. The true innovation lies in the process of how the register data is transferred and displayed. We begin by
Let’s begin with the simplest one: The Cathode Driver. Complex as it may seem, it’s basically just a shift register with an asynchronous reset signal [START]. All of the outputs are in an open-collector configuration. So the output of ‘1’ means ‘Turned off’ while ‘0’ means ‘Turned on’ & ‘Current flows’.
At the negedge of [CLOCK] after the [START] signal, [O15] is switched from 1 to 0. at the next [CLOCK] negedge, [O15] returns 1 and O1 is switched from 1 to 0, and so on, and so forth…
It looks more complicated, But it’s no more than a combination of decoding logic and high current drivers.
The left-bottom-most part is an oscillator, which, when connected to the external LC or crystal circuits, forms an 800kHz clock generator. The clock is further divided into two phases as the system clock. (The Latch-based PMOS dynamic logic utilizes a 2-phase clock).
[ABCDE] are the data lines coming from the ARC. As is labeled: They transmit segment information of the digit that is being shown in a “multiplexed” fashion.
[Qx] are internal timing signals. Them, together with the combination logic in the middle section, give a lot of ‘gating’ signals (illustrated as grey regions on the [Sx] lines).
The output lines [Sx] are active when the corresponding segment information appears on the [ABCDE] lines during the grey sections.
Section 3: Visualizing
That is still too vague to be understood.
Remember in the last article, I mention that -hp- calculators are fully serialized, with several 56-bit shift registers as its internal storage. In each machine cycle, the 56-bit shift register is looped head-to-tail.
We know this because it’s a PMOS dynamic logic. “Dynamic” means all of its registers store information in capacitances. In order to retain this information, any bit in these registers must be read then write-back within a short time period. One way to do this is to do it the “DRAM” way – add a dedicated memory controller, and some FIFO to synchronize with other logic. Here, this method is impractical due to the limited chip area and cost constraints.
HP engineers did it in the “old-fashion” way (I mean… the 50s’ way): form it in a shift-register configuration, and no matter the data is used or not in the current machine cycle, cycle the shift-register so that any bit is sampled by the next NOT gate and get refreshed. By the end of the current machine cycle, we’re back to where we began.
..... .-----------<------------. | | D '-->[ 56bit register ]---' .-----------<------------. | | C '-->[ 56bit register ]---' .-----------------------<-----------------------. | | A '-->[ 56bit register ]-->[Do some calculation]--' .-----------------------<-----------------------. | | B '-->[ 56bit register ]-->[Do some calculation]--'
Adding another 56-bit display buffer is too costly. What’s worse: with the buffer comes additional display control and refresh logic. To top it up, the calculator has its internal data stored in floating point format, if not treated properly, the display formatting routine can be detrimental to the machine’s overall performance; there aren’t any space to retain the place for decimal point, nor any blank-space or negative sign, if we want to somehow insert these characters into the register, we certainly have to reformat the floating-point data format for displaying.
HP engineers did it in a genius way, which not only doesn’t need to do any formatting to raw floating-point
Remember that A is cycled no matter there’s an operation on A or not. In each machine cycle, every nibble in the A register gets captured by the small 5-bit [DISPLAY BUFFER] register at different times (A process that’s been controlled by another 2-bit counter). To determine whether the digit is a decimal or a sign or whatever, there’re two or more additional wires coming from register B that
- To display decimal place or whitespace, the programmer needs to set certain bits in a corresponding register B digit. Usually, decimal place is 4’d6 and whitespace is 4’d9
- When it reaches the two nibbles (in register A!) which represent signs, it displays a negative sign when any of these nibbles is 4′
d9,and displays whitespace when it’s anything else. (Uncertain, correct me if I’m wrong)
- When a 4’bxx1x is in B register, the anode driver immediately shines the decimal point LED, and kathode driver 1820-0854 skips 1 digit forward.
If you’d like to try it out yourself, please be sure to check out the amazing emulator CCE33 (a.k.a. MultiCalc ), which perfectly replicated the behavior of the circuit I described above.
And combine this with the fact that this circuit works by first charging an inductor, then release it. We’re now able to interpret a piece of captured LA data:
- Signal [Start] is set to high briefly at the beginning of a machine cycle.
- Signal [Step] is the clock input of the kathode driver 1820-0854
- Signal [CPH1] is one of the two-phase clocks
- [A#n] is the inferred register MSB data (now on the #nth nibble; It is the data in register “#88” in “Fig.10” that I’ve shown before) It’s only one clock prior to D#n
- [D#n] is what the chip is sending to the anode driver 1820-0853 (now on the #nth nibble)
- The numbers in pink red are what human eyes can actually see (also inferred. I can’t find a way to verify this).
- The orange square shown at the bottom-right corner is signaling for a decimal place. Above it is an additional pulse that ticks the kathode driver before where a pulse normally goes. What happens here is: after all other strokes have been lit, the additional pulse moves the active
kathodeto the next place on the display, lighten the decimal place, and after the charges stored in the decimal place inductor is depleted, the normal pulse further advances to the next digit on the display, and continue displaying the rest decimal data.
Since the LED driver stores no information and is driven at the same speed as the digital system. The refresh rate of this display is very high (3.16kHz). No flicker can be seen, even under the worst operation conditions (such as high vibration,