Fully Serialized Pipeline Digital Signal Processing Techniques

Geesh... announcing it before writing anything, again!

Ahem, anyway, it's very related to (one of) the research work that I've been working on for quite a while. This piece of writing is mainly about designing different types (for example, signed and unsigned integer, IEEE float, etc.) of serialized arithmetic cores, which, in this context, means adder and multiplier.

Although being slow and sometimes occupying much more space to implement, serialized logic does show its amazing properties under specific applications. As mentioned in the previous HP calculator articles, serialized logic can be implemented easily with dynamic logic, which translates to a much smaller silicon footprint.

A Typical 2 Stage NMOS Dynamic Shift Register Design

Also, when pipelined, serialized logic can show no less performance than its parallelized counterparts.

[To be done...]


1 thought on “Fully Serialized Pipeline Digital Signal Processing Techniques”

Leave a Reply

Your email address will not be published. Required fields are marked *